CXL (Compute Express Link)
Compute Express Link (CXL) is an open interconnect on the PCIe physical layer that gives CPUs coherent access to device and expander memory.
Compute Express Link, or CXL, is an open interconnect that runs on the PCIe physical layer and lets processors and devices share memory coherently. One link carries three protocols. CXL.io handles discovery and direct memory access, as PCIe does. CXL.cache lets a device cache host memory, and CXL.mem lets a host treat device memory as cacheable. Type 1 devices use CXL.io and CXL.cache. Type 2 accelerators with local memory use all three, and Type 3 memory expanders use CXL.io and CXL.mem.
CXL 2.0, at 32 GT/s, added single-switch pooling across 2 to 16 hosts. CXL 3.0 doubled the rate to 64 GT/s and added multi-level switching and memory sharing. In a Micron and Intel test, eight 128 GB E3.S modules on a Xeon 6 6900P added 1 TB beside twelve DDR5-6400 channels. On a read-only load, the CXL tier delivered 205 GB/s, against 556 GB/s and lower latency from local DRAM. Interleaving pages across both tiers raised total read-only bandwidth 24 percent. The 6900P supports CXL 2.0 Type 3 devices, and AMD lists CXL 3.1 for EPYC 9006.
Add CXL memory when a CPU workload needs more capacity than the DIMM slots hold, or more bandwidth than the DIMM channels deliver. Keep latency-sensitive data in local DRAM.
Sources
Source | Publisher |
|---|---|
An Introduction to the Compute Express Link (CXL) Interconnect | arXiv |
Micron Technology and Intel | |
AMD |
- Publisher
Micron Technology and Intel
Last verified October 7, 2026.
- CXL meaning
- Compute Express Link
- CXL memory expansion
- CXL.mem
- CXL Type 3 device
- CXL 2.0 vs CXL 3.0
- CXL 3.1
- E3.S CXL module
- CXL memory pooling
- Micron CZ122