ECC memory

ECC memory, short for error-correcting code memory, catches and repairs single-bit errors in RAM before they corrupt a result or crash a process. Each module carries extra memory chips beside the data chips, holding check bits computed from the data. On every read the controller checks those bits, corrects a single flipped bit in place, and flags a double-bit error as uncorrectable rather than passing bad data along.

A DDR4 channel is 64 bits wide, and ECC widens it to 72 bits with a ninth chip per rank. A 32 GB DDR4 ECC module therefore holds about 36 GB of physical DRAM, with the extra 4 GB reserved for check bits and invisible to the operating system. DDR5 splits each module into two 32-bit subchannels, and server ECC modules add 8 check bits to each. Support has to exist in the module, the memory controller, and the board together. Xeon, EPYC, and Threadripper PRO carry it as standard, while most consumer platforms either lack it or leave it unvalidated. The on-die ECC in every DDR5 chip is not the same thing, since it corrects errors inside the DRAM and reports nothing to the host.

Spec it for long simulations and any workload where a silent bit flip yields a wrong answer nobody catches.

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Last verified August 29, 2026.