PCIe lanes

PCIe lanes are the serial data paths that carry traffic between the CPU or chipset and a card or drive. Each lane is one differential pair for transmit and one for receive, and lanes bundle into links written x1, x4, x8, or x16. The count on a slot sets a hard ceiling on what a GPU, NVMe drive, or network adapter can push through it.

Bandwidth per lane doubles each generation: about 1 GB/s per direction on PCIe 3.0, 2 GB/s on 4.0, and 4 GB/s on 5.0. A x16 link at PCIe 5.0 carries roughly 64 GB/s each way, more than a single card usually pulls in practice. Consumer desktop CPUs expose only 20 to 24 lanes, which covers one x16 GPU and a couple of NVMe drives. Server and workstation parts such as EPYC and Threadripper PRO provide up to 128 PCIe 5.0 lanes per socket. Dropping a card from x16 to x8 halves its link but usually costs a few percent in render and game work. Jobs that move gradients between GPUs feel it more.

Count platform lanes before adding a second or third GPU, not slots on the box. Four cards want a server or HEDT platform, not a mainstream desktop chipset.

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Last verified August 29, 2026.