PCIe lanes

PCIe lanes are the serial data paths that carry traffic between the CPU or chipset and a card or drive. PCI Express, the standard behind them, bundles lanes into links written x1, x2, x4, x8, or x16. More lanes mean more bandwidth, and the count on a slot sets a hard ceiling on what a GPU, NVMe drive, or network adapter can push through it. Lanes wired to the CPU reach it directly, while chipset lanes share one uplink.

A GPU usually takes an x16 slot, and a modern M.2 drive uses four lanes. Each lane signals at 8 gigatransfers per second (GT/s) on PCIe 3.0, 16 GT/s on 4.0, and 32 GT/s on 5.0. AMD lists Threadripper WRX90 at 148 lanes, 144 usable, up to 128 of them PCIe 5.0, and TRX50 at 92, 88 usable, up to 80 PCIe 5.0. A one-socket EPYC 9005 server provides 128 PCIe 5.0 lanes, and a two-socket server up to 160. AMD lists 96 PCIe 6.0 lanes for its EPYC 9996.

Add up lanes before adding cards. Four x16 GPUs and four x4 drives need 80 lanes. That takes every PCIe 5.0 lane on TRX50 but fits WRX90 or a one-socket EPYC 9005. Wire GPUs and fast drives to CPU lanes.

Sources

Last verified October 7, 2026.