DDR5 on-die ECC

DDR5 on-die ECC is error correction built into every DDR5 DRAM chip. It corrects single-bit errors inside the chip. Micron lists it as 128b+8b SEC with error check and scrub, a feature DDR4 does not have, and Samsung calls it ODECC. Side-band ECC is separate. It is the ECC memory servers use, where the memory controller computes check bits and the module carries extra bits to store them.

The Linux RAS guide shows the mechanism on a DDR3 ECC module, 64 data bits plus 8 check bits for a 72-bit word, with the controller calculating the code on write and testing it on read. Samsung describes its ECC UDIMM as adding error correction to the structure of a standard UDIMM, working only on a platform that supports it. A plain DDR5 UDIMM has on-die ECC in each chip and no ECC across the module.

Do not count on-die ECC as ECC support. To protect data across the module and the bus, specify ECC RDIMM or ECC UDIMM and confirm the CPU and board list ECC support. Every DDR5 chip has on-die ECC, so it cannot separate one module from another.

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Last verified October 30, 2026.