Memory bus width

Memory bus width is the number of data bits a GPU moves to or from its memory per transfer, quoted as 384-bit or 512-bit. It is also called the memory interface. Peak bandwidth in GB/s equals bus width in bits times the data rate in Gbps, divided by 8. HBM goes wide instead of fast, with 1,024 pins per HBM3E stack and 2,048 on HBM4, per Samsung.

NVIDIA's GB202 GPU, the chip in the RTX PRO 6000 Blackwell, has sixteen 32-bit memory controllers for 512 bits in total. At 28 Gbps that gives 512 x 28 / 8 = 1,792 GB/s, the figure NVIDIA lists. The RTX A6000, a GA102 card, uses twelve such controllers for 384 bits at 16 Gbps, or 768 GB/s. Micron describes a GDDR6 component as 32 DQs, the data pins that make up each chip's share of the bus.

Bus width is fixed per card and can be narrower than the die: the GeForce RTX 3080 runs GA102 at 320 bits. Read it next to the data rate, since either can limit bandwidth. When a card is quoted only in GB/s, multiply by 8 and divide by the data rate to recover the bus width.

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Last verified October 30, 2026.